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W9425G6EH 4 M x 4 BANKS x 16 BITS DDR SDRAM
Table of Contents1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION............................................................................................................. 4 FEATURES .................................................................................................................................... 4 KEY PARAMETERS ...................................................................................................................... 5 PIN CONFIGURATION .................................................................................................................. 6 PIN DESCRIPTION........................................................................................................................ 7 BLOCK DIAGRAM ......................................................................................................................... 8 FUNCTIONAL DESCRIPTION....................................................................................................... 9 7.1 7.2 Power Up Sequence............................................................................................................ 9 Command Function ........................................................................................................... 10
7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 Bank Activate Command ......................................................................................................10 Bank Precharge Command ..................................................................................................10 Precharge All Command ......................................................................................................10 Write Command ...................................................................................................................10 Write with Auto-precharge Command...................................................................................10 Read Command ...................................................................................................................10 Read with Auto-precharge Command ..................................................................................10 Mode Register Set Command ..............................................................................................11 Extended Mode Register Set Command ..............................................................................11
7.2.10 No-Operation Command ......................................................................................................11 7.2.11 Burst Read Stop Command..................................................................................................11 7.2.12 Device Deselect Command ..................................................................................................11 7.2.13 Auto Refresh Command .......................................................................................................11 7.2.14 Self Refresh Entry Command...............................................................................................12 7.2.15 Self Refresh Exit Command .................................................................................................12 7.2.16 Data Write Enable /Disable Command .................................................................................12
7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10
Read Operation ................................................................................................................. 12 Write Operation ................................................................................................................. 13 Precharge .......................................................................................................................... 13 Burst Termination .............................................................................................................. 13 Refresh Operation ............................................................................................................. 13 Power Down Mode ............................................................................................................ 14 Input Clock Frequency Change during Precharge Power Down Mode ............................ 14 Mode Register Operation .................................................................................................. 14
7.10.1 Burst Length field (A2 to A0) ................................................................................................14
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7.10.2 Addressing Mode Select (A3)...............................................................................................15 7.10.3 CAS Latency field (A6 to A4)................................................................................................16 7.10.4 DLL Reset bit (A8) ................................................................................................................16 7.10.5 Mode Register /Extended Mode register change bits (BA0, BA1) ........................................16 7.10.6 Extended Mode Register field ..............................................................................................16 7.10.7 Reserved field ......................................................................................................................16
8.
OPERATION MODE .................................................................................................................... 17 8.1 8.2 8.3 8.4 Simplified Truth Table........................................................................................................ 17 Function Truth Table ......................................................................................................... 18 Function Truth Table for CKE............................................................................................ 21 Simplified Stated Diagram ................................................................................................. 22 Absolute Maximum Ratings............................................................................................... 23 Recommended DC Operating Conditions ......................................................................... 23 Capacitance....................................................................................................................... 24 Leakage and Output Buffer Characteristics ...................................................................... 24 DC Characteristics............................................................................................................. 25 AC Characteristics and Operating Condition..................................................................... 26 AC Test Conditions............................................................................................................ 28 AC Overshoot/Undershoot Specification for Address and Control Pins ........................... 30 Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins ............................ 31 Command Input Timing ..................................................................................................... 32 Timing of the CLK Signals ................................................................................................. 32 Read Timing (Burst Length = 4) ........................................................................................ 33 Write Timing (Burst Length = 4) ........................................................................................ 34 DM, DATA MASK (W9425G6EH) ..................................................................................... 35 Mode Register Set (MRS) Timing ..................................................................................... 36 Extend Mode Register Set (EMRS) Timing....................................................................... 37 Auto-precharge Timing (Read Cycle, CL = 2) ................................................................... 38 Auto-precharge Timing (Read cycle, CL = 2), continued .................................................. 39
9.
ELECTRICAL CHARACTERISTICS ............................................................................................ 23 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9
10.
TIMING WAVEFORMS ................................................................................................................ 32 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9
10.10 Auto-precharge Timing (Write Cycle) ................................................................................ 40 10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) .............................................................. 41 10.12 Burst Read Stop (BL = 8) .................................................................................................. 41 10.13 Read Interrupted by Write & BST (BL = 8)........................................................................ 42 10.14 Read Interrupted by Precharge (BL = 8) ........................................................................... 42 10.15 Write Interrupted by Write (BL = 2, 4, 8) ........................................................................... 43
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10.16 Write Interrupted by Read (CL = 2, BL = 8)....................................................................... 43 10.17 Write Interrupted by Read (CL = 3, BL = 4)....................................................................... 44 10.18 Write Interrupted by Precharge (BL = 8) ........................................................................... 44 10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 45 10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 45 10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 46 10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 46 10.23 Auto Refresh Cycle............................................................................................................ 47 10.24 Precharged/Active Power Down Mode Entry and Exit Timing .......................................... 47 10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing................. 47 10.26 Self Refresh Entry and Exit Timing ................................................................................... 48 11. 12. PACKAGE SPECIFICATION ....................................................................................................... 49 11.1 TSOP 66 lI - 400 mil ......................................................................................................... 49 REVISION HISTORY ................................................................................................................... 50
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1. GENERAL DESCRIPTION
W9425G6EH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words x 4 banks x 16 bits. W9425G6EH delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the personal computer industrial standard, W9425G6EH is sorted into the following speed grades: -4/-5/-6 and -75. The -4 is compliant to the DDR500/CL3 specification. The -5 is compliant to the DDR400/CL3 specification. The -6 is compliant to the DDR333/CL2.5 specification. The -75 is compliant to the DDR266/CL2 specification. All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. Write and Read data are synchronized with the both edges of DQS (Data Strobe). By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9425G6EH is ideal for main memory in high performance applications.
2. FEATURES
* * * * * * * * * * * * * * * * 2.5V 0.2V Power Supply for DDR266/333/400 2.6V 0.1V Power Supply for DDR500 Up to 250 MHz Clock Frequency Double Data Rate architecture; two data transfers per clock cycle Differential clock inputs (CLK and CLK ) DQS is edge-aligned with data for Read; center-aligned with data for Write CAS Latency: 2, 2.5 and 3 Burst Length: 2, 4 and 8 Auto Refresh and Self Refresh Precharged Power Down and Active Power Down Write Data Mask Write Latency = 1 7.8S refresh interval (8K/64 mS refresh) Maximum burst refresh cycle: 8 Interface: SSTL_2 Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant
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3. KEY PARAMETERS
SYMBOL DESCRIPTION
CL = 2 tCK Clock Cycle Time CL = 2.5 CL = 3 tRAS tRC IDD0 IDD1 IDD4R IDD4W IDD5 IDD6 Active Period to Precharge Command
MIN./MAX.
Min. Max. Min. Max. Min. Max. Min. Min. Max. Max. Max. Max. Max. Max.
-4
4 nS 10 nS 36 nS 52 nS 110 mA 150 mA 210 mA 210 mA 190 mA 3 mA
-5
7.5 nS 12 nS 6 nS 12 nS 5 nS 12 nS 40 nS 55 nS 110 mA 150 mA 180 mA 180 mA 190 mA 3 mA
-6
7.5 nS 12 nS 6 nS 12 nS 6 nS 12 nS 42 nS 60 nS 110 mA 150 mA 170 mA 170 mA 190 mA 3 mA
-75
7.5 nS 12 nS 7.5 nS 12 nS 7.5 nS 12 nS 45 nS 67.5 nS 110 mA 150 mA 160 mA 160 mA 190 mA 3 mA
Active to Ref/Active Command Period Operating Current: One Bank Active-Precharge Operating Current: One Bank Active-Read-Precharge Burst Operation Read Current Burst Operation Write Current Auto Refresh Current Self-Refresh Current
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4. PIN CONFIGURATION
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
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5. PIN DESCRIPTION
PIN NUMBER
28 - 32, 35 - 42 26, 27 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 16,51
PIN NAME
A0 - A12
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
Address
Row address: A0 - A12. Column address: A0 - A8. (A10 is used for Auto-precharge) Select bank to activate during row address latch time, or bank to read/write during column address latch time. The DQ0 - DQ15 input and output data are synchronized with both edges of DQS. DQS is Bi-directional signal. DQS is input signal during write operation and output signal during read operation. It is Edgealigned with read data, Center-aligned with write data. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command inputs (along with CS ) define the command being entered. When DM is asserted "high" in burst write, the input data is masked. DM is synchronized with both edges of DQS. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of CLK . CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power for logic circuit inside DDR SDRAM. Ground for logic circuit inside DDR SDRAM.
BA0, BA1 DQ0 - DQ15 LDQS, UDQS
Bank Select Data Input/ Output
Data Strobe
24
CS RAS ,
CAS , WE
Chip Select
23, 22, 21 20, 47
Command Inputs Write Mask Differential Clock Inputs
LDM, UDM CLK,
CLK
45, 46
44 49 1, 18, 33 34, 48, 66 3, 9, 15, 55, 61 6, 12, 52, 58, 64 14, 17, 19, 25, 43, 50, 53
CKE VREF VDD VSS VDDQ VSSQ NC
Clock Enable
Reference Voltage VREF is reference voltage for inputs. Power (+2.5V) Ground
Power (+2.5V) for Separated power from VDD, used for output buffer, to improve noise. I/O Buffer Ground for I/O Buffer No Connection Separated ground from VSS, used for output buffer, to improve noise. No connection (NC pin should be connected to GND or
floating)
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6. BLOCK DIAGRAM
CLK CLK
DLL CLOCK BUFFER
CKE
CONTROL
CS RAS CAS WE
COMMAND
SIGNAL GENERATOR
DECODER COLUMN DECODER COLUMN DECODER
ROW DECODER
A10
CELL ARRAY BANK #0
ROW DECODER
CELL ARRAY BANK #1
A0 A9 A11 A12 BA0 BA1
ADDRESS BUFFER
MODE REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
PREFETCH REGISTER DATA CONTROL CIRCUIT REFRESH COUNTER COLUMN COUNTER
DQ BUFFER
DQ0 DQ15 LDQS UDQS LDM UDM
COLUMN DECODER
COLUMN DECODER
ROW DECODER
CELL ARRAY BANK #2
ROW DECODER
CELL ARRAY BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The cell array configuration is 8912 * 512 * 16
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7. FUNCTIONAL DESCRIPTION
7.1 Power Up Sequence
(1) Apply power and attempt to CKE at a low state ( 0.2V), all other inputs may be undefined 1) Apply VDD before or at the same time as VDDQ. 2) Apply VDDQ before or at the same time as VTT and VREF. Start Clock and maintain stable condition for 200 S (min.). After stable power and clock, apply NOP and take CKE high. Issue precharge command for all banks of the device. Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type. Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8. (An additional 200 cycles(min) of clock are required for DLL Lock before any executable command applied.) Issue precharge command for all banks of the device. Issue two or more Auto Refresh commands. Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low.
(2) (3) (4) (5) (6)
(7) (8) (9)
CLK CLK
ANY CMD
2 Clock min.
Command
PREA tRP
EMRS
2 Clock min.
MRS
2 Clock min.
PREA tRP
AREF tRFC
200 Clock min.
AREF tRFC
MRS
Inputs maintain stable for 200 S min.
Enable DLL
DLL reset with A8 = High
Disable DLL reset with A8 = Low
Initialization sequence after power-up
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7.2
7.2.1
Command Function
Bank Activate Command
( RAS = "L", CAS = "H", WE = "H", BA0, BA1 = Bank, A0 to A12 = Row Address) The Bank Activate command activates the bank designated by the BA (Bank address) signal. Row addresses are latched on A0 to A12 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed.
7.2.2
Bank Precharge Command
( RAS = "L", CAS = "H", WE = "L", BA0, BA1 = Bank, A10 = "L", A0 to A9, A11, A12 = Don't Care) The Bank Precharge command percharges the bank designated by BA. The precharged bank is switched from the active state to the idle state.
7.2.3
Precharge All Command
( RAS = "L", CAS = "H", WE = "L", BA0, BA1 = Don't Care, A10 = "H", A0 to A9, A11, A12 = Don't Care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state.
7.2.4
Write Command
( RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "L", A0 to A8 = Column Address) The write command performs a Write operation to the bank designated by BA. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation.
7.2.5
Write with Auto-precharge Command
( RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "H", A0 to A8 = Column Address) The Write with Auto-precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands.
7.2.6
Read Command
( RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A10 = "L", A0 to A8 = Column Address) The Read command performs a Read operation to the bank designated by BA. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation.
7.2.7
Read with Auto-precharge Command
( RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A10 = "H", A0 to A8 = Column Address) The Read with Auto-precharge command automatically performs the Precharge operation after the Read operation.
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1) READA tRAS (min) - (BL/2) x tCK Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command. 2) tRCD(min) READA < tRAS(min) - (BL/2) x tCK Data can be read with shortest latency, but the internal Precharge operation does not begin until after tRAS (min) has completed. This command must not be interrupted by any other command.
7.2.8
Mode Register Set Command
( RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "L", A0 to A12 = Register Data) The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst Length and DLL reset in the Mode Register. The default values in the Mode Register after powerup are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes.
7.2.9
Extended Mode Register Set Command
( RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L", A0 to A12 = Register data) The Extended Mode Register Set command can be implemented as needed for function extensions to the standard (SDR-SDRAM). These additional functions include DLL enable/disable, output drive strength selection. The default value of the extended mode register is not defined; therefore this command must be issued during the power-up sequence for enabling DLL. Refer to the table for specific codes.
7.2.10 No-Operation Command
( RAS = "H", CAS = "H", WE = "H") The No-Operation command simply performs no operation (same command as Device Deselect).
7.2.11 Burst Read Stop Command
( RAS = "H", CAS = "H", WE = "L") The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation.
7.2.12 Device Deselect Command
( CS = "H") The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command.
7.2.13 Auto Refresh Command
( RAS = "L", CAS = "L", WE = "H", CKE = "H", BA0, BA1, A0 to A12 = Don't Care) AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS- BEFORE-RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The DDR SDRAM requires AUTO Publication Release Date:Apr. 11, 2008 Revision A04
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REFRESH cycles at an average periodic interval of tREFI (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * tREFI.
7.2.14 Self Refresh Entry Command
( RAS = "L", CAS = "L", WE = "H", CKE = "L", BA0, BA1, A0 to A12 = Don't Care) The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command can be issued. Input signals except CKE are "Don't Care" during SELF REFRESH. Since CKE is a SSTL_2 input, VREF must be maintained during SELF REFRESH.
7.2.15 Self Refresh Exit Command
(CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H") The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. The use of SELF REFREH mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra auto refresh command is recommended.
7.2.16 Data Write Enable /Disable Command
(DM = "L/H" or LDM, UDM = "L/H") During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to DQ15.
7.3
Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available after CAS Latency from the issuing of the Read command. The CAS Latency must be set in the Mode Register at power-up. When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated. When the Read with Auto-precharge command is issued, the Precharge operation is performed automatically after the Read cycle then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation.
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7.4 Write Operation
Issuing the Write command after tRCD from the bank activate command. The input data is latched sequentially, synchronizing with both edges(rising & falling) of DQS after the Write command (Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Write with Auto-precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Autoprecharge command cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write operation.
7.5
Precharge
There are two Commands, which perform the precharge operation (Bank Precharge and Precharge All). When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS(max) from the bank activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state.
7.6
Burst Termination
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of (CAS Latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command, the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DM signal must be asserted "high" during tWR to prevent writing the invalided data to the cell array. When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. Refer to the diagrams for Burst termination.
7.7
Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 8192 times (rows) within 64mS. The period between the Auto Refresh command and the next command is specified by tRFC. Self Refresh mode enters issuing the Self Refresh command (CKE asserted "low") while all banks are in the idle state. The device is in Self Refresh mode for as long as CKE held "low". In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8 S and the last distributed Auto Refresh commands must be performed within 7.8 S before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 7.8 S. In Self Refresh mode, all input/output buffers are disabled,
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resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation.
7.8
Power Down Mode
Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode and Precharge Standby Power Down Mode. When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting in low power dissipation (except CKE buffer). Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking CKE "high" can exit this mode. When CKE goes high, a No operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode.
7.9
Input Clock Frequency Change during Precharge Power Down Mode
DDR SDRAM input clock frequency can be changed under following condition: DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency between minimum and maximum operating frequency specified for the particular speed grade. During an input clock frequency change, CKE must be held LOW. Once the input clock frequency is changed, a stable clock must be provided to DRAM before precharge power down mode may be exited. The DLL must be RESET via EMRS after precharge power down exit. An additional MRS command may need to be issued to appropriately set CL etc. After the DLL relock time, the DRAM is ready to operate with new clock frequency.
7.10 Mode Register Operation
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and BA0, BA1 address inputs. The Mode Register designates the operation mode for the read or write cycle. The register is divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL enable/Disable mode). The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the Mode Register Set command must be issued before power operation.
7.10.1 Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2, 4, and 8 words.
A2 A1 A0 BURST LENGTH
0 0 0 0 1
0 0 1 1 x
0 1 0 1 x
Reserved 2 words 4 words 8 words Reserved
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7.10.2 Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both addressing Mode support burst length 2, 4, and 8 words.
A3 ADDRESSING MODE
0 1 7.10.2.1. Addressing Sequence of Sequential Mode
Sequential Interleave
A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following. Addressing Sequence of Sequential Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
2 words (address bits is A0) not carried from A0 to A1 4 words (address bit A0, A1) Not carried from A1 to A2 8 words (address bits A2, A1 and A0) Not carried from A2 to A3
7.10.2.2. Addressing Sequence for Interleave Mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. Addressing Sequence of Interleave Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0
2 words 4 words
8 words
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7.10.3 CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depend on the frequency of CLK.
A6 A5 A4 CAS LATENCY
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Reserved Reserved 2 3 Reserved Reserved 2.5 Reserved
7.10.4 DLL Reset bit (A8) This bit is used to reset DLL. When the A8 bit is "1", DLL is reset. 7.10.5 Mode Register /Extended Mode register change bits (BA0, BA1)
These bits are used to select MRS/EMRS.
BA1 BA0 A12-A0
0 0 1
0 1 x
Regular MRS Cycle Extended MRS Cycle Reserved
7.10.6 Extended Mode Register field
1) DLL Switch field (A0) This bit is used to select DLL enable or disable
A0 DLL
0 1 2) Output Driver Size Control field (A1)
Enable Disable
This bit is used to select Output Driver Size, both Full strength and Half strength are based on JEDEC standard.
A1 OUTPUT DRIVER
0 1
Full Strength Half Strength
7.10.7 Reserved field
* Test mode entry bit (A7) This bit is used to enter Test mode and must be set to "0" for normal operation. * Reserved bits (A9, A10, A11, A12) These bits are reserved for future operations. They must be set to "0" for normal operation. Publication Release Date:Apr. 11, 2008 Revision A04
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W9425G6EH
8. OPERATION MODE
The following table shows the operation commands.
8.1
Simplified Truth Table
COMMAND Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set Extended Mode Register Set No Operation Burst Read Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Power Down Mode Entry Power Down Mode Exit Data Write Enable Data Write Disable DEVICE STATE Idle
(3) (3)
SYM. ACT PRE PREA WRIT WRITA READ READA MRS EMRS NOP BST DSL AREF SELF SELEX
CKEn-1 CKEn H H H X X X X X X X X X X X X H L H
DM
(4)
BA0, BA1 V V X V V V V L, L H, L X X X X X X
A10 V L H L H L H C V X X X X X X
A12, A11, A9-A0 V X X V V V V C V X X X X X X
CS
RAS
CAS
WE
X X X X X X X X X X X X X X X
L L L L L L L L L L L H L L H L H L H L X X
L L L H H H H L L H H X L L X H X H X H X X
H H H L L L L L L H H X L L X H X H X H X X
H L L L L H H L L H L X H H X X X X X X X X
Any
Any Active
(3)
H H H H H H H H H H H L
Active Active
(3)
(3)
Active Idle Idle Any
(3)
Active Any Idle Idle Idle (Self Refresh) Idle/ (5) Active Any (Power Down) Active Active
PD
H
L
X
X
X
X
PDEX WDE WDD Notes:
L H H
H X X
X L H
X X X
X X X
X X X
1. V = Valid
X = Don't Care
L = Low level
H = High level
2. CKEn signal is input level when commands are issued. CKEn-1 signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BA0, BA1 signals. 4. LDM, UDM (W9425G6EH). 5. Power Down Mode can not entry in the burst cycle.
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8.2 Function Truth Table
CS
H L L Idle L L L L L H L L Row Active L L L L L H L L L Read L L L L L H L L L Write L L L L L
(Note 1) CURRENT STATE
RAS
X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L
CAS
X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L
WE
X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L
ADDRESS
X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code
COMMAND
DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS NOP NOP ILLEGAL ILLEGAL Row activating NOP
ACTION
NOTES
3 3
Refresh or Self refresh Mode register accessing NOP NOP Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop Term burst, new read: Determine AP ILLEGAL ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL Term burst, start read: Determine AP Term burst, start read: Determine AP ILLEGAL Term burst, precharging ILLEGAL ILLEGAL
2 2
4 4 3 5
6
3
6, 7 6 3 8
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Function Truth Table, continued
CURRENT STATE
CS
H L L L L L L L L H L L L L L L L L H L L L
RAS
X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L
CAS
X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L
WE
X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L
ADDRESS
X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code
COMMAND
DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS
ACTION
Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after tRP NOP-> Idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after tRP ILLEGAL ILLEGAL NOP-> Row active after tRCD NOP-> Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
NOTES
Read with Autoprecharge
3 3
Write with Autoprecharge
3 3
3 3 3
Precharging
L L L L L H L L L
3 3 3 3
Row Activating
L L L L L
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Function Truth Table, continued
CURRENT STATE
CS
H L L L L L L L L H L L
RAS
X H H H H L L L L X H H H H L L L L X H H H L L X H H H L
CAS
X H H L L H H L L X H H L L H H L L X H H L H L X H H L X
WE
X H L H L H L H L X H L H L H L H L X H L H X X X H L X X
ADDRESS
X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X X X X X X X X X X DSL NOP BST
COMMAND
ACTION
NOP->Row active after tWR NOP->Row active after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Enter precharge after tWR NOP->Enter precharge after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Idle after tRC NOP->Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Row after tMRD NOP->Row after tMRD ILLEGAL ILLEGAL ILLEGAL
NOTES
Write Recovering
READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/WRIT ACT/PRE/PREA
AREF/SELF/MRS/EMRS
3 3 3 3
Write Recovering with Autoprecharge
L L L L L L H L L L L L H L L L L
3 3 3 3
Refreshing
DSL NOP BST READ/WRIT ACT/PRE/PREA/ARE F/SELF/MRS/EMRS
Mode Register Accessing
Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. 2. Illegal if any bank is not idle. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. Illegal if tRCD is not satisfied. 5. Illegal if tRAS is not satisfied. 6. Must satisfy burst interrupt condition. 7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. Must mask preceding data which don't satisfy tWR
Remark: H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data
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Publication Release Date:Apr. 11, 2008 Revision A04
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8.3 Function Truth Table for CKE
CKE n-1
H L Self Refresh L L L L H Power Down L L H H H All banks Idle H H H L H H H Row Active H H H L Any State Other Than Listed Above H
CURRENT STATE
n
X H H H H L X H L H L L L L L X H L L L L L X H
CS
X H L L L X X X X X H L L L L X X H L L L L X X
RAS CAS
X X H H L X X X X X X H L H L X X X H L H L X X X X H L X X X X X X X H L L X X X X H L L X X X
WE
X X X X X X X X X X X X H X X X X X X H X X X X
ADDRESS
X X X X X X X X X X X X X X X X X X X X X X X X INVALID
ACTION
NOTES
Exit Self Refresh->Idle after tXSNR Exit Self Refresh->Idle after tXSNR ILLEGAL ILLEGAL Maintain Self Refresh INVALID Exit Power down->Idle after tIS Maintain power down mode Refer to Function Truth Table Enter Power down Enter Power down Self Refresh ILLEGAL ILLEGAL Power down Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer to Function Truth Table 3 3 2 2 1
Notes:
1. Self refresh can enter only from the all banks idle state. 2. Power Down occurs when all banks are idle; this mode is referred to as precharge power down. 3. Power Down occurs when there is a row active in any bank; this mode is referred to as active power down. Remark: H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data
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8.4 Simplified Stated Diagram
SELF REFRESH
SREF SREFX
IDLE
MRS/EMRS
MODE REGISTER SET
AREF
AUTO REFRESH
PD PDEX ACT
ACTIVE POWERDOWN POWER DOWN
PDEX PD
ROW ACTIVE
BST Read Read
Write
Write
Write
Read
Read
Write A Write A
Read A Read A Read A PRE
Write A
PRE
PRE
Read A
POWER APPLIED
POWER ON
PRE
PRE CHARGE
Automatic Sequence Command Sequence
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9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER SYMBOL RATING UNIT
Input/Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current
VIN, VOUT VDD, VDDQ TOPR TSTG TSOLDER PD IOUT
-0.3 ~ VDDQ + 0.3 -0.3 ~ 3.6 0 ~ 70 -55 ~ 150 260 1 50
V V C C C W mA
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
9.2
Recommended DC Operating Conditions
PARAMETER
Power Supply Voltage (for -5/-6/-75) Power Supply Voltage (for -4) I/O Buffer Supply Voltage (for -5/-6/-75) I/O Buffer Supply Voltage (for -4) Input reference Voltage Termination Voltage (System) Input High Voltage (DC) Input Low Voltage (DC) Differential Clock DC Input Voltage Input Differential Voltage. CLK and CLK inputs (DC) Input High Voltage (AC) Input Low Voltage (AC) Input Differential Voltage. CLK and CLK inputs (AC) Differential AC input Cross Point Voltage Differential Clock AC Middle Point
(TA = 0 to 70C)
SYMBOL
VDD VDD VDDQ VDDQ VREF VTT VIH (DC) VIL (DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC)
MIN.
2.3 2.5 2.3 2.5 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 VREF + 0.31 0.7 VDDQ/2 - 0.2 VDDQ/2 - 0.2
TYP.
2.5 2.6 2.5 2.6 0.50 x VDDQ VREF -
MAX.
2.7 2.7 2.7 2.7 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 VREF - 0.31 VDDQ + 0.6 VDDQ/2 + 0.2 VDDQ/2 + 0.2
UNIT
V V V V V V V V V V V V V V V
NOTES
2 2 2 2 2, 3 2, 8 2 2 15 13, 15 2 2 13, 15 12, 15 14, 15
Notes: Undershoot Limit: VIL (min) = -1.5V with a pulse width < 5 nS
Overshoot Limit: VIH (max) = VDDQ +1.5V with a pulse width < 5 nS VIH (DC) and VIL (DC) are levels to maintain the current logic state. VIH (AC) and VIL (AC) are levels to change to the new logic state.
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9.3 Capacitance
DELTA (MAX.)
0.5 0.25 0.5 -
(VDD = VDDQ = 2.5V 0.2V, f = 1 MHz, TA = 25 C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V)
SYMBOL
CIN CCLK CI/O CNC
PARAMETER
Input Capacitance (except for CLK pins) Input Capacitance (CLK pins) DQ, DQS, DM Capacitance NC Pin Capacitance
MIN.
2.0 2.0 4.0 -
MAX.
3.0 3.0 5.0 1.5
UNIT
pF pF pF pF
Notes: These parameters are periodically sampled and not 100% tested.
The NC pins have additional capacitance for adjustment of the adjacent pin capacitance.
9.4
Leakage and Output Buffer Characteristics
PARAMETER
Input Leakage Current (0V < VIN < VDDQ, All other pins not under test = 0V) Output Leakage Current (Output disabled, 0V < VOUT < VDDQ) Output High Voltage (under AC test load condition) Output Low Voltage (under AC test load condition) Output Minimum Source DC Current Output Minimum Sink DC Current Output Minimum Source DC Current Output Minimum Sink DC Current Half Strength Full Strength
SYMBOL
II (L) IO (L) VOH VOL IOH (DC) IOL (DC) IOH (DC) IOL (DC)
MIN.
-2 -5 VTT +0.76 -15.2 15.2 -10.4 10.4
MAX.
2 5 VTT -0.76 -
UNIT NOTES
A A V V mA mA mA mA 4, 6 4, 6 5 5
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9.5
SYM.
DC Characteristics
PARAMETER -4 -5
110 Operating current: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle Operating current: One Bank Active-Read-Precharge; Burst = 2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once per clock cycle. Precharge Power Down standby current: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM Idle floating standby current: CS > VIH min; All Banks Idle; CKE > VIH min; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DQS and DM Idle standby current: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM Idle quiet standby current: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs stable; Vin > VREF for DQ, DQS and DM Active Power Down standby current: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min Active standby current: CS > VIH min; CKE > VIH min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating current: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=3; tCK = tCK min; IOUT = 0mA Operating current: Burst = 2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle Auto Refresh current: tRC = tRFC min Self Refresh current: CKE < 0.2V Random Read current: 4 Banks Active Read with activate every 20nS, Auto-precharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle
MAX. -6
110
UNIT -75
110
NOTES
IDD0
110
7
IDD1 IDD2P IDD2F
150
150
150
150
7, 9
20
20
20
20
45
45
45
40
7
IDD2N
45
45
45
40
7
IDD2Q IDD3P IDD3N
40 20
40 20
40 20
35 mA 20
7
70
70
70
65
7
IDD4R
210
180
170
160
7, 9
IDD4W IDD5 IDD6 IDD7
210 190 3 300
180 190 3 300
170 190 3 300
160 190 3 300
7 7
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9.6
SYM.
tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL tCK tAC tDQSCK tDQSQ tCH tCL tHP tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tIS tIH tIS tIH tIPW tHZ tLZ tT(SS) tWTR tXSNR tXSRD tREFI tMRD
AC Characteristics and Operating Condition
PARAMETER MIN.
Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto-precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto-precharge Write Recovery + Precharge Time 2 CLK Cycle Time 2.5 3 Data Access Time from CLK, CLK DQS Output Access Time from CLK, CLK Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width CLK Half Period (minimum of actual tCH, tCL) DQ Output Data Hold Time from DQS DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write Command to First DQS Latching Transition Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Control & Address Input Pulse Width (for each input) Data-out High-impedance Time from CLK, CLK Data-out Low-impedance Time from CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to non-Read Command Exit Self Refresh to Read Command Refresh Time (8k/64mS) Mode Register Set Cycle Time 52 60 36 16 16 1 16 8 15 ---4 -0.7 -0.6 0.45 0.45 min (tCL,tCH) tHP -0.5 0.9 0.4 0.4 0.4 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.85 0.6 0.6 0.7 0.7 2.2 -0.7 -0.7 0.5 1 72 200 8
(Notes: 10, 12)
-4 MAX. MIN.
55 70 40 15 15 1 15 10 15 -7.5 6 5 -0.7 -0.6 0.45 0.45 Min, (tCL,tCH) tHP -0.5 0.9 0.4 0.4 0.4 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.72 0.6 0.6 0.7 0.7 2.2 -0.7 -0.7 0.5 2 75 200 10
-5 MAX.
UNIT
NOTES
70000
70000
nS
tCK
18 12 12 12 0.7 0.6 0.4 0.55 0.55 tCK nS
--10 0.7 0.6 0.45 0.55 0.55
16
11
nS 1.1 0.6
1.1 0.6
tCK nS
11
tCK nS 0.6 1.25 tCK
11
0.6 1.15
11 19, 21-23 19, 21-23 20-23 20-23
nS 0.7 0.7 1.5 tCK nS tCK S nS
0.7 0.7 1.5
7.8
7.8
17
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Continued
SYM.
tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL tCK tAC tDQSCK tDQSQ tCH tCL tHP tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tIS tIH tIS tIH tIPW tHZ tLZ tT(SS) tWTR tXSNR tXSRD tREFI tMRD
PARAMETER MIN.
Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto-precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto-precharge Write Recovery + Precharge Time 2 CLK Cycle Time 2.5 3 Data Access Time from CLK, CLK DQS Output Access Time from CLK, CLK Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width CLK Half Period (minimum of actual tCH, tCL) DQ Output Data Hold Time from DQS DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write Command to First DQS Latching Transition Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Control & Address Input Pulse Width (for each input) Data-out High-impedance Time from CLK, CLK Data-out Low-impedance Time from CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to non-Read Command Exit Self Refresh to Read Command Refresh Time (8k/64mS) Mode Register Set Cycle Time 60 72 42 18 15 1 18 12 15 -7.5 6 6 -0.7 -0.6 0.45 0.45 min (tCL,tCH) tHP -0.55 0.9 0.4 0.45 0.45 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 0.75 0.75 0.8 0.8 2.2 -0.7 -0.7 0.5 1 72 200 12
-6 MAX. MIN.
67.5 75 45 20 15 1 20 15 15 -7.5 7.5 7.5 -0.75 -0.75
-75 MAX.
UNIT
NOTES
100000
100000
nS
tCK
18 12 12 12 0.75 0.75 0.5 0.55 0.55 nS
12 12 12 0.7 0.6 0.45 0.55 0.55
16
1.1 0.6
0.6 1.25
0.45 0.45 Min, (tCL,tCH) tHP -0.75 0.9 0.4 0.5 0.5 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 0.9 0.9 1.0 1.0 2.2 -0.75 -0.75 0.5 1 75 200 15
tCK
11
nS 1.1 0.6
tCK nS
11
tCK nS tCK 1.25
11
11 19, 21-23 19, 21-23 20-23 20-23
nS 0.75 0.75 1.5 tCK nS tCK S nS
0.7 0.7 1.5
7.8
7.8
17
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9.7 AC Test Conditions
PARAMETER SYMBOL VALUE UNIT
Input High Voltage (AC) Input Low Voltage (AC) Input Reference Voltage Termination Voltage Differential Clock Input Reference Voltage Input Difference Voltage. CLK and CLK Inputs (AC) Output Timing Measurement Reference Voltage
VIH VIL VREF VTT VR VID (AC) VOTR
VREF + 0.31 VREF - 0.31 0.5 x VDDQ 0.5 x VDDQ Vx (AC) 1.5 0.5 x VDDQ
V V V V V V V
VDDQ VIH min (AC) V SWING (MAX) VREF
VTT
50
VIL max (AC) VSS
T T
Output
Output V(out)
30pF
SLEW = (VIH min (AC) - VILmax (AC)) / T
Timing Reference Load
Notes:
(1) (2) (3) (4) (5) (6) (7) (8) (9) Conditions outside the limits listed under "Absolute Maximum Ratings" may cause permanent damage to the device. All voltages are referenced to VSS, VSSQ.( 2.6V0.1V for DDR500) Peak to peak AC noise on VREF may not exceed 2% VREF(DC). VOH = 1.95V, VOL = 0.35V VOH = 1.9V, VOL = 0.4V The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK and tRC. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF. These parameters depend on the output loading. Specified values are obtained with the output open.
(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed slope.
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(11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., TDQSS = 0.75 x tCK, tCK = 7.5 nS, 0.75 x 7.5 nS = 5.625 nS is rounded up to 5.6 nS.) (12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level. (14) VISO means {VICK(CLK)+VICK( CLK )}/2. (15) Refer to the figure below.
CLK VX CLK VICK VSS VID(AC) VICK VX VX VICK VX VICK VX
VID(AC)
0 V Differential
VISO VISO(min) VSS VISO(max)
(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock. (17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. (18) tDAL = (tWR/tCK) + (tRP/tCK) (19) For command/address input slew rate 1.0 V/nS. (20) For command/address input slew rate 0.5 V/nS and <1.0 V/nS. (21) For CLK & CLK slew rate 1.0 V/nS (single--ended). (22) These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. (23) Slew Rate is measured between VOH(ac) and VOL(ac).
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9.8 AC Overshoot/Undershoot Specification for Address and Control Pins
PARAMETER DDR500 SPECIFICATION DDR400
1.5 V 1.5 V 3.0 V-nS 3.0 V-nS
DDR333
1.5 V 1.5 V 3.6 V-nS 3.6 V-nS
DDR266
1.5 V 1.5 V 4.5 V-nS 4.5 V-nS
Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to Max. area in Figure 1 The area between the undershoot signal and GND must be less than or equal to Max. area in Figure 1
VDD Overshoot 5 4 3 2 Max. area 1 0 -1 -2 -3 -4 -5 Max. amplitude = 1.5V
1.5 V 1.5 V 3.0 V-nS 3.0 V-nS
Max. amplitude = 1.5V
GND
0 0.5 0.68751.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.06.3125 6.5 7.0 Time (nS)
Undershoot
Figure 1: Address and Control AC Overshoot and Undershoot Definition
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9.9 Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins
PARAMETER DDR500 SPECIFICATION DDR400
1.2 V 1.2 V 1.44 V-nS 1.44 V-nS
DDR333
1.2 V 1.2 V 2.25 V-nS 2.25 V-nS
DDR266
1.2 V 1.2 V 2.4 V-nS 2.4 V-nS
Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to Max. area in Figure 2 The area between the undershoot signal and GND must be less than or equal to Max. area in Figure 2
1.2 V 1.2 V 1.44 V-nS 1.44 V-nS
VDD Overshoot 5 4 3 2 Max. area 1 0 -1 -2 -3 -4 -5 0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0 Time (nS) Max. amplitude = 1.2V GND Max. amplitude = 1.2V
Undershoot
Figure 2: DQ/DM/DQS AC Overshoot and Undershoot Definition
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10. TIMING WAVEFORMS
10.1 Command Input Timing
tCK tCK CLK CLK tIS CS tIH tCH tCL
tIS RAS
tIH
tIS CAS
tIH
tIS WE
tIH
tIS A0~A12 BA0,1
tIH
Refer to the Command Truth Table
10.2 Timing of the CLK Signals
CLK CLK tCK CLK CLK VX VX VX VIH VIL tCH tCL VIH VIH(AC) VIL(AC) VIL
tT
tT
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10.3 Read Timing (Burst Length = 4)
tCH CLK
tCL
tCK
CLK
tIS CMD
tIH
READ
tIS
tIH
ADD
Col tDQSCK tDQSCK tRPST Hi-Z Preamble tDQSQ tQH tQH tDQSQ Postamble tDQSQ Hi-Z
CAS Latency = 2 Hi-Z DQS
tDQSCK tRPRE
Output (Data)
Hi-Z tAC tLZ
QA0 DA0
QA1 DA1
QA2 DA2
QA3 DA3 tHZ tDQSCK tDQSCK tRPST
tDQSCK CAS Latency = 3 Hi-Z DQS Preamble tDQSQ Output (Data) Hi-Z tAC tLZ tHZ tQH tQH tDQSQ Postamble tDQSQ Hi-Z tRPRE Hi-Z
QA0 DA0
QA1 DA1
QA2 DA2
QA3 DA3
Notes: The correspondence of LDQS, UDQS to DQ. (W9425G6EH)
LDQS UDQS DQ0~7 DQ8~15
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10.4 Write Timing (Burst Length = 4)
tCH CLK tCL tCK
CLK
tIS
tIH
CMD
WRIT
tIS
tIH
tDSH
tDSS
tDSH
tDSS
ADD
Col
x4, x8 device
tWPRES tWPRE
tDQSH
tDQSL
tDQSH
tWPST
DQS
Preamble tDS tDH Input (Data) tDQSS x16 device tWPRES tWPRE LDQS Preamble tDS tDH
tDS tDH
tDS
Postamble tDH
DA0 tDSH tDQSH
DA1 tDSS tDQSL
DA2 tDSH tDQSH
DA3 tDSS tWPST
Postamble tDS tDH tDS tDH
DQ0~7
tDQSS
DA0
DA1
DA2
DA3
tDSH tWPRES UDQS tWPRE Preamble tDS tDH tDQSH
tDSS tDQSL
tDSH tDQSH
tDSS tWPST
tDS tDH DA1 DA2
tDS Postamble tDH DA3
DQ8~15
DA0 tDQSS
Note: x16 has two DQSs (UDQS for upper byte and LDQS for lower byte). Even if one of the 2 bytes is not used, both UDQS and LDQS must be toggled.
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W9425G6EH
10.5 DM, DATA MASK (W9425G6EH)
C LK
C LK
CMD
W R IT
LD Q S
tD S
tD S
tD H
tD H
LD M tD IP W
D Q 0~D Q 7
D0
D1 tD IP W M asked
D3
UDQS
tD S
tD S
tD H
tD H
UDM tD IP W
D Q 8~D Q 15
D0 M asked
D2
D3 tD IP W
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10.6 Mode Register Set (MRS) Timing
CLK
CLK
tMRD CMD MRS NEXT CMD
ADD
Register Set data
A0 A2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 "0" "0" Reserved "0" "0" "0" "0" Mode Register Set or Extended Mode Register Set "0" Reserved DLL Reset CAS Latency Addressing Mode Burst Length 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A3 0 1 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A8 0 * "Reserved" should stay "0" during MRS cycle. BA1 0 0 1 1 1 BA0 0 1 0 1 A4 0 1 0 1 0 1 0 1 A0 0 1 0 1 0 1 0 1
Burst Length Sequential Reserved 2 4 8 Interleaved Reserved 2 4 8
Reserved
Reserved
Addressing Mode Sequential Interleaved CAS Latency Reserved 2 3 Reserved
2.5 Reserved DLL Reset No Yes MRS or EMRS Regular MRS cycle Extended MRS cycle Reserved
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Publication Release Date:Apr. 11, 2008 Revision A04
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10.7 Extend Mode Register Set (EMRS) Timing
CLK CLK
tMRD CMD EMRS NEXT CMD
ADD
Register Set data
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 "0" "0"
DLL Switch Output Driver
A0 0 1
DLL Switch Enable Disable
A1 "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" Mode Register Set or Extended Mode Register Set Reserved BA1 0 0 1 1 BA0 0 1 0 1 0 1
Output Driver Size Full Strength Half Strength
MRS or EMRS Regular MRS cycle Extended MRS cycle
* "Reserved" should stay "0" during EMRS cycle.
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Publication Release Date:Apr. 11, 2008 Revision A04
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10.8 Auto-precharge Timing (Read Cycle, CL = 2)
1) tRCD (READA) tRAS (MIN) - (BL/2) x tCK
tRAS CLK CLK BL=2 CMD ACT READA AP
tRP
ACT
DQS
DQ
Q0
Q1
BL=4 CMD ACT READA AP ACT
DQS
DQ
Q0
Q1
Q2
Q3
BL=8 CMD ACT
READA
AP
ACT
DQS
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Notes: CL=2 shown; same command operation timing with CL = 2,5 and CL=3 In this case, the internal precharge operation begin after BL/2 cycle from READA command.
Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command.
AP
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10.9 Auto-precharge Timing (Read cycle, CL = 2), continued
2) tRCD/RAP(min) tRCD (READA) < tRAS (min) - (BL/2) x tCK
tRAS CLK CLK BL=2 CMD ACT tRAP tRCD
DQS
tRP
READA
AP
ACT
DQ
Q0
Q1
BL=4 CMD ACT tRAP tRCD DQS READA AP ACT
DQ
Q0
Q1
Q2
Q3
BL=8 CMD ACT tRAP tRCD DQS READA AP ACT
DQ
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Notes: CL2 shown; same command operation timing with CL = 2.5, CL=3.
In this case, the internal precharge operation does not begin until after tRAS (min) has command.
AP
Represents the start of internal precharging.
The Read with Auto-precharge command cannot be interrupted by any other command.
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Publication Release Date:Apr. 11, 2008 Revision A04
W9425G6EH
10.10 Auto-precharge Timing (Write Cycle)
CLK CLK tDAL BL=2 CMD WRITA AP ACT
DQS
DQ
D0
D1 tDAL
BL=4 CMD WRITA AP ACT
DQS
DQ
D0
D1
D2
D3 tDAL
BL=8 CMD WRITA
AP
ACT
DQS
DQ
D0
D1
D2
D3
D4
D5
D6
D7
The Write with Auto-precharge command cannot be interrupted by any other command.
AP
Represents the start of internal precharging .
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Publication Release Date:Apr. 11, 2008 Revision A04
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10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8)
CLK CLK
CMD
ACT
READ A
READ B
READ C
READ D
READ E
tRCD ADD
Row Address
tCCD
COl,Add,A Col,Add,B
tCCD
Col,Add,C
tCCD
Col,Add,D
tCCD
Col,Add,E
DQS
DQ
QA0
QA1
QB0
QB1
QC0
10.12 Burst Read Stop (BL = 8)
CLK CLK
CMD
READ
BST
CAS Latency = 2 DQS
CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5
CAS Latency = 3 DQS
CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5
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W9425G6EH
10.13 Read Interrupted by Write & BST (BL = 8)
CLK CLK CAS Latency = 2 CMD READ BST WRIT
DQS
DQ
Q0
Q1
Q2
Q3
Q4
Q5
D0
D1
D2
D3
D4
D5
D6
D7
Burst Read cycle must be terminated by BST Command to avoid I/O conflict.
10.14 Read Interrupted by Precharge (BL = 8)
C LK C LK
CMD
READ
PR E
C AS Latency = 2 DQS
C AS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5
C AS Latency = 3 DQS
C AS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5
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10.15 Write Interrupted by Write (BL = 2, 4, 8)
CLK CLK
CMD
ACT
WRIT A
WRIT B
WRIT C
WRIT D
WRIT E
tRCD ADD
Row Address
tCCD
COl. Add. A Col.Add.B
tCCD
tCCD
tCCD
Col. Add. E
Col. Add. C
Col. Add. D
DQS
DQ
DA0
DA1
DB0
DB1
DC0
DC1
DD0
DD1
10.16 Write Interrupted by Read (CL = 2, BL = 8)
CLK CLK
CMD
WRIT
READ
DQS
DM
tWTR
DQ D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Data must be masked by DM
Data masked by READ command, DQS input ignored.
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Publication Release Date:Apr. 11, 2008 Revision A04
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10.17 Write Interrupted by Read (CL = 3, BL = 4)
CLK CLK
CMD
WRIT
READ
DQS
DM
tWTR DQ D0 D1 D2 D3 Q0 Q1 Q2 Q3
Data must be masked by DM
10.18 Write Interrupted by Precharge (BL = 8)
CLK CLK
CMD
WRIT
PRE
ACT
tWR
DQS
tRP
DM
DQ
D0
D1
D2
D3
D4
D5
D6
D7
Data must be masked by DM
Data masked by PRE command, DQS input ignored.
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Publication Release Date:Apr. 11, 2008 Revision A04
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10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2)
tCK = 100 MHz
CLK CLK tRC(b) tRC(a) tRRD CMD ACTa ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRP(b) tRP(a) READAa READAb ACTa tRRD ACTb
DQS Preamble CL(a) DQ
Q0a
Postamble
Preamble
Postamble
CL(b)
Q1a Q0b Q1b
ACTa/b : Bank Act. CMD of bank a/b READAa/b : Read with Auto Pre.CMD of bank a/b APa/b : Auto Pre. of bank a/b
APa
APb
10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4)
CLK CLK tRC(b) tRC(a) tRRD CMD ACTa ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRP(b) tRP(a) READAa READAb ACTa tRRD ACTb
DQS Preamble CL(a) DQ
Q0a
Postamble CL(b)
Q1a Q2a Q3a Q0b Q1b Q2b Q3b
ACTa/b : Bank Act. CMD of bank a/b READAa/b : Read with Auto Pre.CMD of bank a/b APa/b : Auto Pre. of bank a/b
APa
APb
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Publication Release Date:Apr. 11, 2008 Revision A04
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10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2)
CLK CLK tRC(a) tRRD CMD AC Ta AC Tb tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRCD(c) tRAS(c) tRCD(d) tRAS(d) tRP tRRD ACTc tRRD R EADAa ACTd tRRD R EAD Ab AC Ta READ Ac
DQS Pream ble C L(a) DQ
Q 0a
Postam ble CL(b)
Q 1a
Pream ble
Q0b
Q 1b
ACTa/b/c/d : Bank Act. C M D of bank a/b/c/d READ Aa/b/c/d : Read w ith Auto Pre.CM D of bank a/b/c/d APa/b/c/d : Auto Pre. of bank a/b/c/d
APa
APb
10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4)
CLK CLK tR C (a ) tR R D CMD ACTa tR C D (a ) tR A S (a ) tR C D (b ) tR A S (b ) tR C D (c ) tR A S (c ) tR C D (d ) tR A S (d ) tR P (a ) ACTb tR R D READAa ACTc tR R D READAb ACTd tR R D READAc ACTa READAd
DQS P re a m b le C L (a ) DQ
Q 0a
C L (b )
Q1a Q 0a Q 1a Q2a
C L (c )
Q 3a Q0b Q 1b Q 2b Q3b
A C T a /b /c /d : B a n k A c t. C M D o f b a n k a /b /c /d R E A D A a /b /c /d : R e a d w ith A u to P re .C M D o f b a n k a /b /c /d A P a /b /c /d : A u to P re . o f b a n k a /b /c /d
APa
APb
APc
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Publication Release Date:Apr. 11, 2008 Revision A04
W9425G6EH
10.23 Auto Refresh Cycle
CLK CLK
CMD
PREA
NOP
AREF
NOP
AREF
NOP
CMD
tRP
tRFC
tRFC
Note: CKE has to be kept "High" level for Auto-Refresh cycle.
10.24 Precharged/Active Power Down Mode Entry and Exit Timing
CLK CLK tIH CKE tIS tCK tIH tIS
Precharge/Activate Note 1,2 Entry CMD CMD NOP Exit NOP CMD NOP
Note:
1. If power down occurs when all banks are idle, this mode is referred to as precharge power down. 2. If power down occurs when there is a row active in any bank, this mode is referred to as active power down.
10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing
CLK CLK CMD
NOP
NOP
Frequency Change Occurs here
NOP tIS
DLL RESET
NOP
NOP
CMD
CKE
tRP
200 clocks
Minmum 2 clocks required before changing frequency
Stable new clock before power down exit
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Publication Release Date:Apr. 11, 2008 Revision A04
W9425G6EH
10.26 Self Refresh Entry and Exit Timing
CLK CLK tIS tIH tIS
tIH CKE
CMD
PREA
NOP tRP
SELF
SELEX
NOP
CMD
Entry
Exit
tXSNR tXSRD
SELF
SELFX
NOP
ACT
NOP
READ
NOP
Entry
Exit
Note: If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.
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Publication Release Date:Apr. 11, 2008 Revision A04
W9425G6EH
11. PACKAGE SPECIFICATION
11.1 TSOP 66 lI - 400 mil
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Publication Release Date:Apr. 11, 2008 Revision A04
W9425G6EH
12. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A01 A02
Dec. 12, 2007 Jan. 04, 2008
All 5, 25 5, 26 23 5, 25 9
Formally data sheet Revise -4 speed grade Max.IDD4R/IDD4W value from 190mA to 210mA Revise -5 speed grade Max. CLK cycle time tCK value from 10nS to 12nS Change VDDQ max from VDD to 2.7V Modify -4 speed grade DC Characteristics IDD6 parameter value from 5mA to 3mA Add figure to illustrate Initialization sequence after power-up Revise overshoot/undershoot pulse width Before VIH (max.) = -1.2V with a pulse width < 3 nS After VIH (max.) = -1.5V with a pulse width < 5 nS Before VIL (min.) = VDDQ +1.2V with a pulse width < 3 nS After VIL (min.) = VDDQ +1.5V with a pulse width < 5 nS Revise input setup/hold time tIS/tIH parameters with skew rate dependency of AC characteristics table
A03
Feb. 21, 2008
A04
Apr. 11, 2008 23
26, 27, 29
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date:Apr. 11, 2008 Revision A04

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